Device-Level Modeling and Synthesis of High-Performance by Jesús Ruiz-Amaya, Manuel Delgado-Restituto, Ángel

By Jesús Ruiz-Amaya, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez

This e-book provides types and tactics to layout pipeline analog-to-digital converters, compensating for machine inaccuracies, in order that high-performance specifications should be met inside of brief layout cycles. those types are in a position to shooting and predicting the habit of pipeline information converters inside under half-a-bit deviation, as opposed to transistor-level simulations. consequently, a ways fewer version iterations are required around the layout cycle. versions defined during this publication effectively are expecting temporary behaviors, that are key to the functionality of discrete-time platforms and consequently to the functionality of pipeline facts converters.

  • Describes effective systems for heirarchical top-down layout of pipeline converters;
  • offers new methodologies to lessen bottom-up iterations, via inherent embedding of transistor-level parameters, corresponding to parasitic capacitances, transconductances, and saturation currents;
  • Provides mathematical information of behavioral versions, comprises descriptions of the synthesis tools and linked instruments and illustrates types via case reviews supported via silicon prototypes.

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Additional info for Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs

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4) Transistor-level parasitics, as well as sizes for transistors and power consumption are accurately estimated thanks to a set of Matlab routines. These routines include valuable information on the technology using look-up table techniques. 5) The bottom-up iterations are drastically reduced since the parasitics and transistorlevel parameters are well estimated from the beginning. In fact, only fine tuning is required after the post-layout parasitics are established. 6) Both high- and low-level specifications mapping are combined in a single synthesis procedure, which basically allows us to consider the dependences between the different abstraction levels and improve the synthesis results.

Typically, this task is reserved for experienced designers who decide which is the best solution in accordance with the knowledge acquired from previous designs. Once the topology has been selected, the converter specifications must be mapped onto high-level specifications for the basic building blocks (high-level specifications mapping). A simulation-based optimization procedure is normally used for this purpose. As performance evaluator, a behavioural simulator is the most common approach as it provides fast performance evaluations and an acceptable resolution.

This technique requires the addition of two more switch sets, which enable the OTA to commutate between the two stages. The advantage afforded by this is that the number of amplifiers required is halved and power consumption is significantly reduced. However, this technique has two main drawbacks. First, the additional switches introduce a series of resistances which, in combination with the amplifier input capacitance, affect the settling behaviour of the stage. Second, the non-zero input voltage of the amplifier due to the OTA finite DC gain and offset voltage is never reset.

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